1. Field of the Invention
The present invention relates to wireless communication systems and, in particular, to wireless communication systems based on the IEEE 802.16 specifications.
However, the invention also applies in general to any communication system in which the carrier and sampling clock frequencies of all the signals transmitted between the base station and the subscriber equipment are locked to a same and unique reference clock frequency derived from a reference oscillator of the base station.
2. Description of Related Art
As a matter of fact, in wireless communication networks, a base station serves a number of users that are located in its coverage area. This is the case in the current mobile cellular networks including GSM, third-generation mobile cellular networks (UMTS, CDMA 2000, . . . ), wireless local area networks (WiFi) and broadband wireless access networks (WiMax). Most of recent wireless communication standards are based on the multicarrier transmission technique known as orthogonal frequency-division multiplexing (OFDM). Indeed, the IEEE 802.11a specifications for WiFi are based on 64-carrier OFDM and the mode of IEEE 802.16 specifications adopted by WiMax is based on 256-carrier OFDM.
In a number of system specifications including WiMax, the transmit center frequency, receive center frequency and the symbol clock frequency at the base station must be derived from the same reference oscillator. The subscriber station or equipment may use this relationship between the symbol clock frequency and the base station transmit center frequency to avoid explicitly estimating the receive center frequency. The receive carrier frequency at the subscriber equipment may be indeed derived from the symbol clock frequency, and in this case a simple timing estimator is sufficient to perform timing and carrier frequency estimation.
In the IEEE 802.16 specifications, both the transmit center frequency and the symbol clock frequency of the subscriber equipment must be synchronized and locked to the base station with a precision better than 2% of the OFDM sub-carrier spacing. During the synchronization period, the subscriber equipment must acquire frequency synchronization within the specified tolerance before attempting any uplink transmission. During normal operation, the subscriber equipment must track the frequency changes and defer any transmission if synchronization is lost.
Reference is now made to FIG. 1 which illustrates a simplified block diagram of a conventional symbol timing recovery device of subscriber equipment highlighting the position of the symbol timing functions within the overall receiver structure.
As illustrated in FIG. 1, the timing recovery device, denoted by reference 10, is placed between the radio frequency part 12 and the digital modem 14 of a subscriber equipment or station, such as a mobile cellular phone terminal, and is partly incorporated within the modem 14.
The timing recovery device comprises essentially a phase locked loop (PLL) circuit 16 comprising a timing error detector 18, a loop filter 20 and a voltage-controlled crystal oscillator (VCXO) 22.
In this conventional scheme, the PLL circuit is used to control a clock generator 24, the output of which delivers a receive sampling clock RX sampling clock and a transmit sampling clock TX sampling clock to an analog-to-digital converter circuit 26 and to a digital-to-analog converter circuit 28, respectively, which communicate with a digital demodulator 17 and a digital modulator 19.
In addition, the clock generator 24, which is composed of a PLL and a direct digital synthesis DDS clock, provides the radio frequency part 12 of the equipment with a reference clock RF part reference clock in order to control this radio frequency part accordingly.
As a matter of fact, the voltage-controlled oscillator VCXO adjusts the frequency and, hence, the phase according to the loop filter output. This frequency, which is locked to the base station, is used to generate the sampling frequency for the analog-to-digital (A/D) converter 26 and the carrier frequency of the RF receiver of the radio frequency part 12. On the other hand, it is also used to generate the sampling frequency for digital-to-analog (D/A) converter 28 and the carrier frequency of the RF transmitter of the radio frequency part 12.
The loop filter is employed to limit the variance of the noise in the error signal generated by the error detector 18. Hence, its bandwidth determines the performance of the PLL when noise is present. The smaller the bandwidth of the loop filter, the smaller is the variance of the noise in the error signal.
On the other hand, the tracking ability of the PLL is also determined by the loop filter bandwidth. A larger bandwidth enables the PLL to track rapidly changing phase. Therefore, the bandwidth of loop filter is chosen as a compromise between robustness to noise and tracking ability.
With this scheme, the sampling frequency and carrier frequency are adjusted by controlling the reference clock via the VCXO. This solution requires costly analog components like VCXO and DDS clock.